This disclosure relates generally to semiconductor fabrication techniques and, in particular, to structures and methods for fabricating stacked field-effect transistor (FET) devices.
In a typical complementary metal-oxide-semiconductor (CMOS) layout, ninety percent of the time a first transistor is connected to at least a second transistor. For example, a drain of an n-type transistor is connected to the drain of a p-type transistor to form an inverter. Other arrangements, such as connections between the drain of a first transistor connected to the source of a second transistor, a drain of a first transistor connected to the drain of a second transistor, or a source of a first transistor connected to the source of a second transistor are also considered, where the first and second transistors may be any combination of n-type or p-type transistors. Hence, stacking transistors one on top of another is attractive in order to reduce the area required to accommodate the multiple transistors. However, with normal planar transistors, stacking is difficult and may involve bonding.